View LT3420EDD-1_4284451.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt3420/lt3420-1 1 3420fb , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. *protected by u.s. patents including 6518733. applicatio s u features descriptio u typical applicatio u digital camera flash unit film camera flash unit high voltage power supplies charges 220 f to 320v in 3.7 seconds from 5v (lt3420) charges 100 f to 320v in 3.5 seconds from 5v (lt3420-1) charges any size photoflash capacitor supports operation from two aa cells or any supply from 1.8v to 16v controlled peak switch current: 1.4a (lt3420) 1.0a (lt3420-1) controlled input current: 840ma (lt3420) 450ma (lt3420-1) uses standard transformers efficient flyback operation (>75% typical) adjustable output automatic refresh charge complete indicator no high voltage zener diode required no output voltage divider required small 10-lead msop package small 10-lead (3mm 3mm) dfn package photoflash capacitor chargers with automatic refresh the lt ? 3420/lt3420-1 charge high voltage photoflash capacitors quickly and efficiently. designed for use in both digital and film cameras, these devices use a flyback topology to achieve efficiencies up to four times better than competing flash modules. a unique adaptive off-time control algorithm* maintains current-limited continuous mode transformer operation throughout the entire charge cycle, eliminating the high inrush current often found in modules. the lt3420/lt3420-1 output voltage sensing scheme* monitors the flyback voltage to indirectly regulate the output voltage, eliminating an output resistor divider or discrete zener diode. this feature allows the capacitor to be held at a fully charged state without excessive power consumption. automatic refresh (which can be defeated) allows the capacitor to remain charged while consuming an average input current of about 2ma, at a user-defined refresh rate. a logic high on the charge pin initiates charging, while the done pin signals that the capacitor is fully charged. the lt3420/lt3420-1 are available in 10-lead msop and (3mm 3mm) dfn packages. figure 1. high charge rate lt3420 photoflash circuit v bat 1.8v to 6v input current 350ma 3420 f01 + v cc charge done sec r ref lt3420 v bat r fb sw c t gnd c2 4.7 f 0.1 f c1 4.7 f v cc 2.5v to 10v charge done 51.1k t1 1:12 320v 3,4 5,6 8 1 2k d1 c1, c2: 4.7 f, x5r or x7r, 10v c3: rubycon 220 f photoflash capacitor t1: tdk srw10epc-u01h003 flyback transformer d1: vishay gsd2004s sot-23 dual diode. diodes connected in series c3 220 f 330v photoflash capacitor 4 9 8 10 5 1 7 6 3 2 danger high voltage operation by high voltage trained personnel only figure 2. small size lt3420-1 photoflash circuit 3420 f02 + v cc charge done sec r ref lt3420-1 v bat r fb sw c t gnd c2 4.7 f 0.1 f c1 4.7 f v bat 1.8v to 6v input current 450ma v cc 2.5v to 6v charge done 60.4k t1 1:10 (3mm tall) 320v 3 4 5 6 2k d1 c1, c2: 4.7 f, x5r or x7r, 6.3v c3: rubycon 100 f photoflash capacitor t1: kijima musen sbl-5.6s-2 d1: vishay gsd2004s sot-23 dual diode. diodes connected in series c3 100 f 330v photoflash capacitor 4 9 8 10 5 1 7 6 3 2
2 lt3420/lt3420-1 3420fb 1 2 3 4 5 r ref v bat r fb v cc gnd 10 9 8 7 6 c t charge done sec sw top view ms package 10-lead plastic msop parameter conditions min typ max units minimum operating voltage, v cc 2.2 2.5 v maximum operating voltage, v cc 16 v v cc uvlo hysteresis 40 mv minimum v bat voltage 1.6 1.8 v maximum v bat voltage 16 v v bat uvlo hysteresis 275 mv r ref threshold voltage 0.98 1.00 1.02 v 0.975 1.025 v r ref pin bias current v rref = 0v, switching 2 4 a v rfb = v bat C 0.2v (note 4) quiescent current v rref = 1.1v, not switching 90 130 a quiescent current in shutdown v charge = 0v, v in = 3.3v 0.01 1 a consult ltc marketing for parts specified with wider operating temperature ranges. v cc voltage .............................................................. 16v v bat voltage ............................................................ 16v sw voltage (note 2) lt3420 ................................................................ 38v lt3420-1 ............................................................ 50v sec current ...................................................... 200ma r fb current ........................................................... 3ma r ref voltage ........................................................... 2.5v charge voltage ...................................................... 16v ct voltage .............................................................. 1.5v absolute axi u rati gs w ww u (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v bat = 3.3v, v charge = v cc unless otherwise noted. (note 3) t jmax = 125 c, ja = 100 c/w, jc = 45 c/w (4-layer board) top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 c t charge done sec sw r ref v bat r fb v cc gnd 11 order part number lt3420edd LT3420EDD-1 t jmax = 125 c, ja = 43 c/w, jc = 3 c/w exposed pad is gnd (pin 11) and must be soldered to pcb package/order i n for m atio n w u u dd part marking lbjw lbjx order part number ms part marking ltyh ltajg lt3420ems lt3420ems-1 done voltage .......................................................... 16v current into done pin .......................................... 1ma maximum junction temperature .......................... 125 c operating ambient temperature range (note 3) .............................................. C 40 c to 85 c storage temperature range ................. C 40 c to 125 c lead temperature (soldering, 10 sec) (for ms package only) ..................................... 300 c
lt3420/lt3420-1 3 3420fb v bat (v) 2 time (s) 3420 g03 45 3 6 10 8 6 4 2 0 v out charged from 50v to 320v t a = 25 c figure 1 circuit unless otherwise noted. c out = 220 f c out = 100 f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: rated breakdown with lt3420 in power delivery mode and power switch off. note 3: the lt3420/lt3420-1 are guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c parameter conditions min typ max units primary side current limit lt3420 (note 5) 1.20 1.4 1.60 a lt3420-1 (note 5) 0.75 0.9 1.05 a secondary side current limit lt3420 (note 5) 20 40 50 ma lt3420-1 (note 5) 5 15 25 ma leakage blanking pulse width lt3420 200 ns lt3420-1 0 ns refresh timer charge/discharge current v ct = 0.75v 1.5 2.5 3.5 a refresh timer upper threshold 0.9 1.0 1.1 v refresh timer lower threshold 0.45 0.5 0.55 v switch v cesat lt3420, sw = 1a (note 5) 220 340 mv lt3420-1, sw = 0.5a (note 5) 130 230 mv switch leakage current v sw = 38v (lt3420), v sw = 50v (lt3420-1) 0.01 1 a charge input voltage high 1.5 v charge input voltage low 0.2 v charge pin bias current v charge = 3v 4.5 15 a v charge = 0v 0.01 0.1 a done output signal high 100k from v cc to done 3.3 v done output signal low 33 a into done pin 100 200 mv electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v bat = 3.3v, v charge = v cc unless otherwise noted. (note 3) operating temperature range are assured by design, characterization and correlation with statistical process controls. note 4: bias current flows out of r fb pin. note 5: current limit and v cesat guaranteed by design and/or correlation to static test for dd package. typical perfor a ce characteristics uw output voltage in refresh mode, lt3420 output voltage in refresh mode, lt3420 charge time, lt3420 temperature ( c) C50 v out (v) 100 3420 g01 050 335 330 325 320 315 310 305 300 295 C25 25 75 125 figure 1 circuit v cc = 3.3v v bat = 3.3v v in (v) 2.5 v out (v) 3420 g02 4.0 3.5 3.0 5.5 5.0 4.5 6.0 figure 1 circuit v cc = v in v bat = v in t a = 25 c 335 330 325 320 315 310 305 300 295 graphs apply to both the lt3420 and lt3420-1 unless otherwise noted.
4 lt3420/lt3420-1 3420fb output voltage in refresh mode, lt3420-1 temperature ( c) C50 v out (v) 100 3420 g04 050 335 330 325 320 315 310 305 300 295 C25 25 75 125 figure 2 circuit v cc = 3.3v v bat = 3.3v v in (v) 2.5 v out (v) 5.5 3420 g05 5.0 3.0 4.0 3.5 4.5 6.0 figure 2 circuit v cc = v in v bat = v in t a = 25 c 335 330 325 320 315 310 305 300 295 v bat (v) 2 time (s) 6 3420 g06 3 4 5 10 8 6 4 2 0 figure 2 circuit v out charged from 50v to 320v t a = 25 c c out = 100 f c out = 40 f output voltage in refresh mode, lt3420-1 charge pin input current primary current limit, lt3420 secondary current limit, lt3420 charge time, lt3420-1 charge pin voltage (v) 2 current ( a) 10 8 6 4 2 0 57 10 3420 g07 34 6 89 t a = 25 c temperature ( c) C50 current (a) 3420 g08 0 50 100 1.7 1.5 1.3 1.1 0.9 C25 25 75 125 temperature ( c) C50 current (ma) 100 3420 g09 050 60 55 50 45 40 35 30 25 20 C25 25 75 125 efficiency of figure 1 circuit, lt3420 primary current limit, lt3420-1 secondary current limit, lt3420-1 efficiency (%) 3420 g10 90 80 70 60 50 40 v out (v) 100 200 300 50 150 350 250 v cc = v bat = v in v in = 3.3v v in = 5v t a = 25 c temperature ( c) C50 current (a) 3420 g11 0 50 100 1.2 1.1 1.0 0.9 0.8 C25 25 75 125 temperature ( c) C50 current (ma) 100 3420 g12 050 35 30 25 20 15 10 5 C25 25 75 125 graphs apply to both the lt3420 and lt3420-1 unless otherwise noted. typical perfor a ce characteristics uw
lt3420/lt3420-1 5 3420fb typical perfor a ce characteristics uw efficiency for figure 2 circuit, lt3420-1 input current, lt3420 v cc minimum operating voltage quiescent current in refresh mode v bat minimum operating voltage input current, lt3420-1 efficiency (%) 3420 g13 90 80 70 60 50 40 v out (v) 100 200 300 50 150 350 250 v cc = v bat = v in v in = 3.3v v in = 5v t a = 25 c average input current (ma) 3420 g14 1000 900 800 700 600 500 v out (v) 100 200 300 50 150 350 250 figure 1 circuit v cc = v bat = 3.3v t a = 25 c v out (v) 50 300 average input current (ma) 350 400 450 500 600 100 150 200 250 3420 g15 300 350 550 figure 2 circuit v cc = v bat = 3.3v t a = 25 c v cc (v) 2.5 quiescent current ( a) 10 3420 g16 5.5 8.5 140 120 100 80 60 4.0 7.0 t a = 25 c temperature ( c) C50 v cc pin voltage (v) 100 3420 g17 050 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 C25 25 75 125 v + v C enable voltage is hysteretic temperature ( c) C50 v bat pin voltage (v) 100 3420 g18 050 C25 25 75 125 2.0 1.8 1.6 1.4 1.2 1.0 v + v C enable voltage is hysteretic graphs apply to both the lt3420 and lt3420-1 unless otherwise noted.
6 lt3420/lt3420-1 3420fb uu u pi fu ctio s r ref (pin 1): reference resistor pin. place a resistor (r2) from the r ref pin to gnd. 2k is recommended. v bat (pin 2): battery voltage input. this pin should be connected to the power supply or battery, which supplies power to transformer t1. must be locally bypassed. r fb (pin 3): feedback resistor pin. place a resistor (r1) from the sw pin to the r fb pin. set r1 according to the following formula: r r n rnv v sec out d 1 2 14 2 2 =++ [] (. ? ) ( ) (lt3420) r r n rnv v sec out d 1 2 2 2 =++ [] ()( ) (lt3420-1) v out : desired output voltage n: transformer turns ratio r sec : transformer secondary resistance v d : diode forward voltage drop r2: resistor from the r ref pin to gnd. 2k is a typical choice v cc (pin 4): input supply pin. must be locally bypassed with a 4.7 f or larger ceramic capacitor. gnd (pin 5): ground. tie directly to local ground plane. sw (pin 6): switch pin. this is the collector of the internal npn power switch. minimize the metal trace area con- nected to this pin to minimize emi. sec (pin 7): transformer secondary pin. tie one end of the transformer secondary to this pin. take care to use the correct phasing of the transformer (refer to figures 1 and 2). done (pin 8): done output pin. open collector npn output. done is pulled low whenever the chip is delivering power to the output and goes high when power delivery stops. charge (pin 9): charge pin. drive charge high (1.5v or more) to commence charging of the output capacitor. drive to 0.2v or less to put the part in shutdown mode. c t (pin 10): refresh timer capacitor pin. place a capacitor from the c t pin to gnd to set the refresh timer sample rate according to the following formula: c t = 2.5 ? 10 C6 ? t refresh t refresh : desired refresh period in seconds. exposed pad (pin 11) (dd package only): gnd. must be soldered to local ground plane on pcb.
lt3420/lt3420-1 7 3420fb 3420 f04 C + C + C + + C r s q one- shot 1v reference 5 8 9 2 3 1 6 7 master latch qq s r done v bat v bat r fb sw gnd r ref sec v cc v cc v out charge chip enable ct block enable q5 q3 c3 c2 c1 q4 q2 q1 d3 a3 a2 a1 refresh timer one- shot enable 10 4 + C lt3420-1 r2 r1 primary secondary + 20mv 10mv driver power delivery block d1 c4 photoflash capacitor 0.02 ? 0.66 ? t1 1:10 figure 3. block diagram, lt3420 3420 f03 C + C + C + + C r s q one- shot 1v reference 5 8 9 2 3 1 6 7 master latch qq s r done v bat v bat r fb sw gnd r ref sec v cc v cc v out charge chip enable ct block enable q5 q3 c3 c2 c1 q4 q2 q1 d3 a3 a2 a1 refresh timer one- shot enable 10 4 + C lt3420 r2 r1 primary secondary + 0.014 ? 0.25 ? 20mv 10mv driver power delivery block t1 1:12 d1 c4 photoflash capacitor block diagra s w figure 4. block diagram, lt3420-1
8 lt3420/lt3420-1 3420fb overview the following text focuses on the operation of the lt3420. the operation of the lt3420-1 is nearly identical with the differences discussed at the end of this section. the lt3420 uses an adaptive on-time/off-time control scheme to provide excellent efficiency and precise control of switching currents. please refer to figure 3 for the fol- lowing overview of the parts operation. at any given instant, the master latch determines which mode the lt3420 is in: charging or refresh. in charging mode, the circuitry enclosed by the smaller dashed box is enabled, providing power to charge photoflash capacitor c1. the output volt- age is monitored via the flyback pulse on the primary of the transformer. when the target output voltage is reached, the charging mode is terminated and the part enters the refresh mode. in refresh mode, the power delivery block is disabled, reducing quiescent current, while the refresh timer is en- abled. the refresh timer simply generates a user program- mable delay, after which the part reenters the charging mode. once in the charging mode, the lt3420 will again provide power to the output until the target voltage is reached. figure 5 is an oscillograph photo showing both the initial charging of the photoflash capacitor and the subse- quent refresh action. the upper waveform is the output voltage. the middle waveform is the voltage on the c t pin. the lower waveform shows the input current. the mode of the part is indicated below the photo. the user can defeat the refresh timer and force the part into charging mode by toggling the charge pin operatio u (high low high). the low to high transition on the charge pin fires a one-shot that sets the master latch, putting the part in charging mode. bringing charge low puts the part in shutdown. the refresh timer can be programmed to wait indefinitely by simply grounding the c t pin. in this configuration, the lt3420 will only reenter the charging mode by toggling the charge pin. power delivery block the power delivery block consists of all circuitry enclosed by the smaller dashed box in figure 3. this circuit block contains all elements needed for charging and output voltage detection. to better understand the circuit opera- tion, follow the subsequent description of one cycle of operation and refer to figure 6. assume that initially there is no current in the primary or secondary of the trans- former, so the output of comparator a1 is low, while that of a2 is high (note the small offset voltages at the inputs of a1 and a2). the sr latch is thus set and the power npn switch, q1, is turned on. current increases linearly in the primary of the transformer at a rate determined by the v bat voltage and the primary inductance of the transformer. as the current builds up, the voltage across the 14m ? resistor increases. when this voltage exceeds the 20mv offset voltage of a1, the output of a1 goes high, resetting the sr latch and turning off q1. the current needed to reset the latch is approximately 1.4a (~20mv/14m ? ). when q1 turns off, the secondary side current quickly jumps from zero current to the primary side current di- vided by n (the turns ratio of transformer t1). in this ex- ample, the peak secondary current is 116ma (1.4a/12). diode d1 now conducts, providing power to the output. since a positive voltage exists across the secondary wind- ing of the transformer, the secondary current decreases linearly at a rate determined by the secondary inductance and the output voltage (neglecting the diode voltage drop). when the secondary side current drops below 40ma (10mv/0.25 ? ), the output of a2 goes high, setting the sr latch and turning on q1. the initial primary current is sim- ply the minimum secondary current times n, in this case 0.48a (40ma ? 12) . q1 will now remain on until the pri- mary current again reaches 1.4a. this cycle of operation repeats itself, automatically adjusting the on and off times figure 5. demonstrating 3 operating modes of lt3420: shutdown, charging and refresh of photoflash capacitor v out 100v/div mode i in 1a/div v ct 1v/div 1s/div 3420 f05 shutdown charging refresh
lt3420/lt3420-1 9 3420fb of q1 so that the peak current of q1 is 1.4a and the mini- mum secondary current is 40ma (typical values). the previously described charging cycle must be halted when the output voltage reaches the desired value. the lt3420 monitors the output voltage via the flyback pulse on the sw pin. when q1 turns off, the secondary side conducts current turning on diode d1. since the diode is conducting and the sec pin is at nearly ground, the voltage across the secondary is nearly equal to v out . the voltage across the primary is therefore close to v out /n. a current proportional to v out /n flows through r1 and into the r fb pin. the current flows out of the r ref pin through a resis- tor creating a ground referred voltage. when this voltage exceeds an internal 1v reference voltage, the output of comparator a3 goes high which resets the master latch. the q output of the master latch goes low, disabling the entire power delivery block and enabling the refresh timer. leakage spike blanking another function of the lt3420 is leakage spike blanking when the power switch, q1, turns off. right after q1 turns off, a one-shot turns on q2 for 200ns (typ). with q2 on, comparator a3 is disabled. this function may prevent a3 from false tripping on the leakage inductance spike on the sw pin. in practice, the pnp transistor q3 filters out the leakage spike. refresh timer when the refresh timer is enabled, a 2.5 a current source is switched on, charging up the external timing capacitor, figure 6b. switching waveforms with v out = 300v, v cc = v bat = 3.3v figure 6a. switching waveforms with v out = 100v, v cc = v bat = 3.3v operatio u c3, from its initial voltage towards 1v. when the voltage on c3 reaches 1v, the polarity of the current source changes and 2.5 a discharges c3. when the voltage on c3 reaches 0.5v, the refresh timer sends a set pulse to the master latch, which puts the lt3420 into the charging mode. interface/control the charge pin serves two functions. the first is to enable or shutdown the part depending on the level of the pin (high = enable, low = shutdown). the second is to force the part into the charging mode (low high transi- tion). the lt3420 also has a done pin, which signals whether or not the part is done charging the photoflash capacitor. the done pin is an open collector npn switch (q5) so an external pull-up resistor is needed. whenever the part is in charging mode, done will be low. done will go high when the charging mode is complete. both the charge and done pins can be easily interfaced to a microprocessor in a digital or film camera. lt3420-1 differences the lt3420-1 has different primary and secondary cur- rent limit levels. the primary current limit level of the lt3420-1 is 1a (typ) and the secondary current limit is 15ma (typ). the lt3420-1 has no leakage spike blanking which causes no problems since the pnp transistor, q3, provides adequate filtering. finally, the breakdown voltage of the sw pin of the lt3420-1 is higher at 50v. i sw 1a/div v sw 20v/div i sec 200ma/div 2 s/div 3420 f06a 2 s/div 3420 f06b i sw 1a/div v sw 20v/div i sec 200ma/div
10 lt3420/lt3420-1 3420fb component selection choosing the right transformer the flyback transformer plays a key role in any lt3420/ lt3420-1 application. a poorly designed transformer can result in inefficient operation. linear technology corpora- tion has worked with a number of transformer manufactur- ers to develop specific transformers for use with the lt3420/lt3420-1. these predesigned transformers are sufficient for a large majority of the applications that may be encountered. in some cases, the reader may choose to design his own transformer or may simply be curious about the issues involved in designing the transformer. the fol- lowing is a brief discussion of the issues relating to trans- former design. transformer turns ratio the turns ratio for the transformer, n, should be high enough so that the absolute maximum voltage rating for the npn power switch is not exceeded. when the power switch turns off, the voltage on the collector of the switch (sw pin) will fly up to the output voltage divided by n plus the battery voltage (neglecting the voltage drop across the rectifying diodes). this voltage should not exceed the 38v (lt3420) or 50v (lt3420-1) breakdown rating of the power switch. choose the minimum n by the following formula. n v v lt n v v lt min out bat min out bat ? 38 3420 50 3420 1 C () C () for an lt3420 design, a 5v battery voltage and a 330v output results in a n min of 10 so a turns ratio of 10 or greater should be used. transformer primary inductance a flyback transformer needs to store substantial amounts of energy in the core during each switching cycle. the transformer, therefore, will generally require an air gap. the use of an air gap in the core makes the energy storage ability, or inductance, much more stable with temperature and variations in the core material. most core manufactur- ers will supply standard sizes of air gaps with a given type of core, resulting in different a l values. a l is the induc- tance of a particular core per square turns of winding. to get a certain inductance, simply divide the desired induc- tance by the a l value and take the square root of the result to find the number of turns needed on the primary of the transformer. the lt3420/lt3420-1 detect the output voltage via the flyback pulse on the sw pin. since this can only occur while the power switch is off, an important criteria is that the value of the primary inductance of the transformer be larger than a certain minimum value. the switch off time should be 500ns or larger for the lt3420 and 350ns or larger for the lt3420-1. the minimum inductance can be calculated with the following formula: l v nn lt l v nn lt pri out pri out ? 500 10 14 004 3420 350 10 10 0015 3420 1 9 9 ?? ?( . C . ) () ?? ?(.C. ) () C C v out : target output voltage n: transformer turns ratio transformer leakage inductance the leakage inductance of the transformer must be care- fully minimized for both proper and efficient operation of the part. the dc voltage rating of the sw pin on the lt3420 is 38v while on the lt3420-1 it is 50v. these ratings are for dc blocking voltages only and additional precautions applicatio s i for atio wu uu
lt3420/lt3420-1 11 3420fb must be taken into account for the dynamic blocking voltage capabilities of the lt3420/lt3420-1. the dynamic blocking voltage capability of both parts is 38v. table 1 summarizes the various breakdown voltages of the sw pin for both parts. table 1. sw pin voltage ratings part sw pin dc rating sw pin dynamic rating lt3420 38v 38v lt3420-1 50v 38v figure 7 shows what to examine in a new transformer design to determine if the specifications for the sw pin are met. the first leakage inductance spike labeled a must not exceed the dynamic rating of the sw pin. if it does exceed the rating, then the transformer leakage inductance must be lowered. the flyback waveform after the initial spike labeled b must not exceed the dc rating of the sw pin. if it does exceed the rating, then the turns ratio of the transformer must be lowered. in measuring the voltage on the sw pin, care must be taken in minimizing the ground loop of the voltage probe. careless probing will result in inaccurate readings. applicatio s i for atio wu uu note also the magnitude of the initial current spike in the primary of the transformer labeled c when the power switch turns on. if the leakage inductance is lowered to a very low level, the internal capacitances of the transformer will be high. this will result in the initial spike of current in the primary becoming excessively high. the level of c should be kept to 4a or less in a typical design for both the lt3420 and lt3420-1. please note that by inserting a loop of wire in the primary to measure the primary current, the leakage inductance of the primary will be made artificially high. this may result in erroneous voltage measurements on the sw pin. the measurements shown in figure 7 should be made with both v out and v bat at the maximum levels for the given application. this results in the highest voltage and current stress on the sw pin. transformer secondary capacitance the total capacitance of the secondary should be mini- mized for both efficient and proper operation of the lt3420/ lt3420-1. since the secondary of the transformer under- goes large voltage swings (approaching 600v p-p ), any capacitance on the secondary can severely affect the i pri v sw 3420 f07 0a 0v a b must be less than 38v for both the lt3420 and lt3420-1 must be less than 4a for both the lt3420 and lt3420-1 must be less than 38v for the lt3420 must be less than 50v for the lt3420-1 c figure 7. new transformer design check (not to scale)
12 lt3420/lt3420-1 3420fb applicatio s i for atio wu u u efficiency of the circuit. in addition, the effective capaci- tance on the primary is largely dominated by the actual secondary capacitance. this is simply a result of any secondary capacitance being multiplied by n 2 when re- flected to the primary. since n is generally 10 or higher, a small capacitance of 10pf on the secondary is 100 times larger, or 1.0nf, on the primary. this capacitance forms a resonant circuit with the primary leakage inductance of the transformer. as such, both the primary leakage induc- tance and secondary side capacitance should be mini- mized. table 2 shows various predesigned transformers along with relevant parameters. contact the individual trans- former manufacturer for additional information or customization. table 2a. predesigned transformers, lt3420 turns l size part ratio ( h) lxwxh (mm) vendor srw10epc 1:12 24 10.9x10.8x5.2 tdk -u01h003 (847) 803-6100 www.components.tdk.com 6375-t108 1:12 15 10.8x9.5x3.6 sumida (847) 956-0666 www.sumida.com sbl-6.4 1:12 17.5 10.3x6.4x5.2 kijima musen 852-2489-8266 kijimahk@netvigator.com table 2b. predesigned transformers, lt3420-1 turns l size part ratio ( h) lxwxh (mm) vendor sbl-5.6s-2 1:10 15 5.6x8.5x3.0 kijima musen 852-2489-8266 kijimahk@netvigator.com ldt565630t 1:10.2 14.5 5.8x5.8x3.0 tdk -002 (847) 803-6100 www.components.tdk.com diode selection the rectifying diode(s) should be low capacitance type with sufficient reverse voltage and forward current rat- ings. the peak reverse voltage that the diode(s) will see is approximately: v pk-r + () vnv out bat (? )?. 165 the peak current of the diode is simply: i i pk-sec pk-sec = = ? 14 3420 10 3420 1 . () . () a n lt a n lt for the circuit of figure 1 with v bat of 3.3v, v pk-r is 590v and i pk-sec is 116ma. table 3 shows various diodes that can work with the lt3420/lt3420-1. these are chosen for low capacitance and high reverse blocking voltage. use the appropriate number of diodes to achieve the necessary reverse breakdown voltage. table 3 max reverse capacitance part voltage (v) (pf) vendor gsd2004s 2x300 5 vishay (dual diode) (402) 563-6866 www.vishay.com bas21 250 1.5 philips semiconductor (single diode) (800) 234-7381 www.philips.com mmbd3004s 2x300 5 diodes inc. (805) 446-4800 www.diodes.com
lt3420/lt3420-1 13 3420fb capacitor selection the v bat and v cc decoupling capacitors should be multi- layer ceramic type with x5r or x7r dielectric. this insures adequate decoupling across wide ambient temperature ranges. a good quality ceramic capacitor is also recom- mended for the timing capacitor on the c t pin. avoid y5v or z5u dielectrics. selectively disabling the lt3420/lt3420-1 the lt3420/lt3420-1 can be disabled at any time, even during the charge phase. this may be useful when a digital camera enters a sensitive data acquisition phase. figure 8 illustrates this feature. midway through the charge cycle, the charge pin is brought low, which disables the part. after the sensitive data operation is complete, the charge pin is brought high and the charging operation continues. measuring ef?iency measuring the ef?ciency of a circuit designed to charge large capacitive loads is a dif?cult issue, particularly with photo?ash capacitors. the ideal way to measure the ef?ciency of a capacitor charging circuit would be to ?nd the energy delivered to the output capacitor (0.5 ? c ? v 2 ) and divide it by the total input energy. this method does not work well here because photo?ash capacitors are far from ideal. among other things, they have relatively high leakage currents, large amounts of dielectric absorption, and signi?cant voltage coef?cients. a much more accu- rate, and easier, method is to measure the ef?ciency as a function of the output voltage. in place of the photo?ash capacitor, use a smaller, high quality capacitor, reducing errors associated with the non-ideal photo?ash capacitor. using an adjustable load, the output voltage can be set anywhere between ground and the maximum output voltage. the ef?ciency is measured as the output power (v out ? i out ) divided by the input power (v in ? i in ). this method also provides a good means to compare various charging circuits since it removes the variability of the photo?ash capacitor from the measurement. the total ef?ciency of the circuit, charging an ideal capacitor, would be the time average of the given ef?ciency curve, over time as v out changes. adjustable input current with many types of modern batteries, the maximum allowable current that can be drawn from the battery is limited. this is generally accomplished by active circuitry or a polyfuse. different parts of a digital camera may require high currents during certain phases of operation and very little at other times. a photo?ash charging circuit should be able to adapt to these varying currents by drawing more current when the rest of the camera is drawing less, and vice-versa. this helps to reduce the charge time of the photo?ash capacitor, while avoiding the applicatio s i for atio wu uu figure 8. halting the charge cycle at any time v out 50v/div charge no charge 0.5s/div 3420 f08 5v/ div v charge
14 lt3420/lt3420-1 3420fb risk of drawing too much current from the battery. the input current to the lt3420/lt3420-1 circuit can be adjusted by driving the charge pin with a pwm (pulse width modulation) signal. the microprocessor can adjust the duty cycle of the pwm signal to achieve the desired level of input current. many schemes exist to achieve this function. once the target output voltage is reached, the pwm signal should be halted to avoid overcharging the photo?ash capacitor, since the signal at the charge pin overrides the refresh timer. a simple method to achieve adjustable input current is shown in figure 9. the pwm signal has a frequency of 1khz. when on is logic high, the circuit is enabled and the charge pin is driven by the pwm signal. when the target output voltage is reached, done goes high while charge is also high. the output of a1 goes high, which forces charge high regardless of the pwm signal. the part is now in the refresh mode. once the refresh period is over, the done pin goes low, allowing the pwm signal to drive the charge pin once again. this function can be easily implemented in a microcontroller. figure 10 shows the input current for the lt3420 and lt3420-1 as the duty cycle of the pwm signal is varied. applicatio s i for atio wu uu figure 9. simple logic for adjustable input current figure 10. input current as duty cycle is varied a1 a3 3420 f09 a2 to lt3420 circuit charge done on 1khz pwm signal input current (ma) duty cycle (%) 90 3420 f10 10 800 lt3420 lt3420-1 0 30 50 70 400 200 600
lt3420/lt3420-1 15 3420fb board layout the high voltage operation of the lt3420/lt3420-1 demands careful attention to board layout. you will not get advertised performance with careless layout. fig- ures 11 and 12 show the recommended component placement. keep the area for the high voltage end of the secondary as small as possible. note the larger than minimum spacing for all high voltage nodes. this is necessary to meet the breakdown specifications for the circuit board. if the photoflash capacitor is placed far from the lt3420/lt3420-1 circuit, place a small (20nf- 50nf) ceramic capacitor with sufficient voltage rating close to the part. this insures adequate bypassing. remember that lethal voltages are present in this circuit. use caution when working with the circuit. figure 11. suggested layout (ms10 package) 3420 f11 charge done c3 c1 c2 + C r2 r1 d1a d1b photoflash capacitor v out v bat v cc gnd t1 applicatio s i for atio wu uu figure 12. suggested layout (dd package) 3420 f12 charge done c3 c1 c2 + C r2 r1 d1a d1b photoflash capacitor v out v bat v cc gnd t1
16 lt3420/lt3420-1 3420fb 3420 ta01 + v cc charge done sec r ref lt3420 v bat r fb sw c t gnd c2 4.7 f c3 0.1 f c1 4.7 f v bat 1.8v to 6v v cc 2.5v to 10v r1 52.3k 2 4 9 8 10 5 36 7 1 2 4 9 8 10 5 36 7 1 t1 1:12 320v 3, 4 5, 6 8 1 r2 2k d1 c1, c2, c4, c5, c6, c7: 4.7 f, x5r or x7r, 10v t1-t3: tdk srw10epc-u01h003 flyback transformer d1-d3: vishay gsd2004s sot-23 dual diode. diodes connected in series q1: 2n3904 or equivalent * can charge any size photoflash capacitor ** use as many slave chargers as needed. danger high voltage operation by high voltage trained personel only 650 f* 350v photoflash capacitor v cc charge done sec r ref lt3420 v bat r fb sw c t gnd c5 4.7 f c4 4.7 f v bat t2 1:12 3, 4 5, 6 3, 4 5, 6 8 1 2 4 9 8 10 5 36 7 1 1 d2 slave** charger master charger slave** charger v cc charge done sec r ref lt3420 v bat r fb sw c t gnd c7 4.7 f c6 4.7 f v bat t3 1:12 8 1 d3 r4 100k r3 100k v cc v cc q1 2n3904 charge typical applicatio s u professional charger uses multiple lt3420 circuits in parallel to charge large photoflash capacitors quickly
lt3420/lt3420-1 17 3420fb typical applicatio s u 3420 ta02 + v cc charge done sec r ref lt3420 v bat r fb sw c t gnd c2 4.7 f c3 0.1 f c1 4.7 f v bat 1.8v to 5v v cc 2.5v to 10v charge done r1 47.5k t1* 1:12 300v 2 1 3 5 r2 2k d1 c1: 4.7 f, x5r or x7r, 6.3v c2: 4.7 f, x5r or x7r, 10v c4: rubycon 220 f photoflash capacitor d1: vishay gsd2004s sot-23 dual diode. diodes connected in series t1: kijima musen sbl-6.4 * maximum ambient temperature of 60 c dictated by transformer danger high voltage operation by high voltage trained personel only c4 220 f 330v photoflash capacitor 4 9 8 10 5 1 7 6 3 2 v out (v) 50 efficiency (%) 90 80 70 60 50 40 100 150 200 250 3420 ta03 300 350 v in = 3.3v v cc = v bat = v in v in = 5v efficiency lt3420 photoflash charging circuit uses small transformer
18 lt3420/lt3420-1 3420fb package descriptio u ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc
lt3420/lt3420-1 19 3420fb dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd10) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc
20 lt3420/lt3420-1 3420fb part number description comments ltc ? 3400/ltc3400b 600ma (i sw ), 1.2mhz, synchronous step-up v in = 0.85v to 5v, v out(max) = 5v, i q = 19 a/300 a, dc/dc converters i sd = <1 a, thinsot tm package ltc3401/ltc3402 1a/2a (i sw ), 3mhz, synchronous step-up v in = 0.5v to 5v, v out(max) = 6v, i q = 38 a, i sd = <1 a, dc/dc converters ms package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in = 2.7v to 6v, v out(min) = 0.8v , i q = 20 a, dc/dc converters i sd = <1 a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in = 2.5v to 5.5v, v out(min) = 0.6v, i q = 20 a, dc/dc converters i sd = <1 a, thinsot package ltc3407 dual 600ma (i out ), 1.5mhz, synchronous step-down 95% efficiency, v in = 2.5v to 5.5v, v out(min) = 0.6v, i q = 40 a, dc/dc converter i sd = <1 a, thinsot package ltc3411 1.25a (i out ), 4mhz, synchronous step-down 95% efficiency, v in = 2.5v to 5.5v, v out(min) = 0.8v, i q = 60 a, dc/dc converter i sd = <1 a, ms package ltc3425 5a (i sw ), 8mhz, multiphase synchronous step-up 95% efficiency, v in = 0.5v to 4.5v, v out(min) = 5.25v, i q = 12 a, dc/dc converter i sd = <1 a, qfn package ltc3440/ltc3441 600ma/1a (i out ), 2mhz/1mhz, synchronous buck-boost 95% efficiency, v in = 2.5v to 5.5v, v out(min) = 2.5v, i q = 25 a, dc/dc converters i sd = <1 a, ms package lt3464 85ma (i sw ), constant off-time, high efficiency v in = 2.3v to 10v, v out(max) = 34v, i q = 25 a, i sd = <0.5 a, step-up dc/dc converter with integrated schottky thinsot package and output disconnect ltc3467 1.1a (i sw ), 1.3mhz, high efficiency step-up v in = 2.4v to 16v, v out(max) = 40v, i q = 1.2ma, i sd = <1 a, dc/dc converter thinsot package ltc3468/ltc3468-1/ photoflash capacitor charger in thinsot fast photoflash charge times; 4.6sec for lt3468, 5.5sec for ltc3468-2 lt3468-1, 5.7sec for lt3468-2 thinssot is a trademark of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2002 lt/lt 0305 rev b ? printed in usa related parts lt3420-1 photoflash circuit uses tiny (3mm tall) transformer 3420 ta04 + v cc charge done sec r ref lt3420-1 v bat r fb sw c t gnd c2 4.7 f 0.1 f c1 4.7 f v bat 1.8v to 6v v cc 2.5v to 6v charge done 60.4k t1 1:10.2 320v 8 5 4 1 2k d1 c1, c2: 4.7 f, x5r or x7r, 6.3v c3: rubycon 100 f photoflash capacitor t1: tdk ldt565630t-002 flyback transformer d1: vishay gsd2004s sot-23 dual diode. diodes connected in series danger high voltage operation by high voltage trained personel only c3 100 f 330v photoflash capacitor 4 9 8 10 5 1 7 6 3 2 v bat (v) 2 time (s) 6 3420 ta05 3 4 5 10 8 6 4 2 0 v out charged from 50v to 320v c out = 100 f c out = 40 f charge time u typical applicatio

▲Up To Search▲

Price & Availability of LT3420EDD-1

	To Download LT3420EDD-1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .